The present invention relates to an apparatus for recovering clock, and in particular to an apparatus for recovering clock for data received asynchronously or synchronously, especially in relatively small baud length or bit length packets.
Conventionally, phase lock loops (PLLs) are utilized for recovering clock for data to be received in digital format. A disadvantage of PLLs is that a relatively high number of preamble data bits is required for the PLL to acquire a proper clock signal, and constant reinforcement for this clock signal (e.g. transition line encoding) must be contained within the data to prevent the PLL from unlocking from a dominant frequency detected from the preamble. PLLs typically require about 10 or more bits of preamble for adequately locking onto a dominant frequency. Examples of PLLs are found in U.S. Pat. Nos. 4,385,396; 4,677,648; and 3,980,820, the disclosures of which are incorporated herein by reference.
The inclusion of an excessively long preamble and transition line encoding to maintain a PLL clock can significantly increase a bit rate for a system. In the case of an asynchronous packetized system for transmitting telephone signals along a bus or ring, the overhead can easily exceed 50% of the total signal. Specifically, for a packet of data containing eight bits with eight preamble bits and 4B5B transition line encoding, the actual data content of any packet is less than half of the signal bits actually transported.
Other circuits, see e.g. Tanabe et al., U.S. Pat. No. 4,672,639, acquire phase repeatedly to "build" a confidence factor for selecting a proper clock phase. That approach allows the circuit to maintain clocking of data even when preamble bits are missed. Building a confidence factor, however, requires the sampling of many bits over a period of time before a clock is selected. This increases the necessary transmission speed which increases power requirements and increases costs.